The present invention relates generally to integrated circuits ("ICs") and more specifically to an IC with increased reverse bias breakdown for a given doping profile.
Planar structures with high surface doping are desired for the islands of an IC because of low leakage, ease of manufacture and reproducibility. Where a well of one conductivity type has been created in an island of the other conductivity type to produce a PN junction, the crowding of the field at the PN junction at the surface of the island reduces reverse bias breakdown voltage for a given doping profile.
In ICs having such PN junctions, a depletion layer forms in the island when a reverse bias is applied to the PN junction, which layer has a depth directly (a) proportional to the reverse bias applied to the junction and (b) inversely proportional to 1/2 to 1/3 power of the doping concentration of the island. At high voltages the doping concentration of the island is small to avoid avalanche breakdown, and the layer of depletion beneath the PN junction may be quite deep under a reverse bias. To prevent the depletion layer from extending downwardly into the supporting substrate, the island must be thick, which results in an undesirable loss of packing density in the IC.
This reduction in island doping concentration also increases the series resistance of the PN junction in the forward direction and limits operating temperature.
It is known to use an appropriately biased field plate overlying at least the surface junction of a planar PN junction to increase the reverse bias breakdown voltage of the junction to thereby deplete the area of the island contiguous to and laterally beyond the surface PN junction. Such field plates mitigate, but do not completely eliminate, the degradation of planar breakdown relative to the breakdown of a plane junction having the same doping profile.
As is shown, e.g., by the Hartman, et al. U.S. Pat. No. 4,608,590, it is also known in gated diode devices to bias the insulated conductive substrate for the island to induce a field in the island and the insulator underlying the island, to thereby deplete the island directly between the PN junction and the substrate (i.e., the JFET channel), and thereby pinch off the conduction of current through the device.
Breakdown occurs in planar PN junctions along the sides of the junction near the island surface or, where there is a field plate, near the island surface around the end of the field plate where the field is crowded. Because breakdown does not generally occur between the PN junction and the bottom of the island, breakdown is not improved by depletion of this area.
Hartman, et al. neither disclose nor teach the use of the combination of field plate and substrate bias to totally deplete the island in the area under the field plate, i.e., an area substantially broader than the depletion area directly under the PN junction and encompassing the area where breakdown usually occurs. Inasmuch as an increase in the width of the field plate increases breakdown where total depletion is obtained, the lateral extension of total depletion may be used to increase breakdown to a value in excess of the plane breakdown of a PN junction with the same doping profile.
It is accordingly an object of the present invention to provide a novel method and PN junction structure with breakdown greater than breakdown that of the same junction and field plate when the substrate is at island voltage.
It is another object of the present invention to provide a novel method and PN junction structure with breakdown greater than breakdown of a plane junction with the same doping profile.
It is still another object of the present invention to provide a novel method and PN junction structure in which the island doping can be increased for a given breakdown, thus increasing the maximum operating temperature.
These and other objects of the present invention are attained by using the combined bias of an insulated field plate and substrate to totally deplete the entire portion of the island under the field plate before the critical field for avalanche is reached. In one aspect, the present invention combines a biasing which merges the depletion layers from a field plate and a biased substrate over an area sufficiently enlarged by enlargement of the field plate to increase breakdown beyond the breakdown for a plane PN junction with the same doping profile.
Where the same or electrically interconnected substrate is used for both vertical and lateral isolation (i.e., at both the bottom and sides of the island), the biasing of the laterally isolating substrate (i.e., at the sides of the island) may present corner breakdown problems in particular island geometries. For example, the potential difference between the biased substrate and either the island contact or a terminal interconnect may add to the field passing through the island adjacent a lateral edge thereof, i.e., the "corner" of the island. This increase in field strength may result in undesirable avalanche at a reduced terminal voltage. A more detailed explanation of corner breakdown may be obtained by reference to my copending application Ser. No. 08/053,343 filed concurrently herewith and assigned to the assignee hereof, the disclosure of said application being herein incorporated by reference.
It is accordingly another object of the present invention to provide a novel IC and method for enhancing breakdown by reducing corner breakdown, and more particularly by the separate biasing of the vertical and lateral island isolating substrates.
Other objects, advantages and novel features of the present invention will become apparent from the claims and from the following detailed description of preferred embodiments of the invention when considered in conjunction with the accompanying drawings.